AI Patent Summary

Patent Document
#US5212780A
United States Patent 11
Abstract
The RAM includes sub-arrays having odd and even memory locations, respectively. A data move instruc- tion results in externally generated row and column address signals which are decoded to cause a first mem- ory location, in one of the sub-arrays, to be selected and data to be read. The next memory location in sequence, in the other of the sub-arrays, is then selected, without necessity for an additional set of row address signals, for writing of the read information. The row decoder in- cludes row indexing circuitry actuatable upon receipt of a shift signal signifying that the first memory location is in the last column of a given row. When the shift signal is received, the write location is automatically selected to be in the succeeding row.
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Patent Classification & AI Product Mapping
Authoritative patent classification definitions mapped to real-world technology domains and commercial product categories.
CPC G06F5/00
Confidence: Medium
Official Definition
Methods or arrangements for data conversion without changing the order or content of the data handled
PHYSICS > COMPUTING OR CALCULATING; COUNTING > ELECTRIC DIGITAL DATA PROCESSING
AI Technology & Product Mapping
Technology Domain:
Memory Management & Data Routing
Product Category:
RAM Controllers & Memory Subsystems
Plain-English Summary:
Techniques for converting or moving data formats and locations without altering the actual content or logical sequence of the data.
Relation to Claims:
The patent discloses a mechanism to move data between odd and even memory locations internally using a data move instruction, which aligns with internal data conversion and transfer without changing content.
CPC G06F5/01
Confidence: High
Official Definition
Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
PHYSICS > COMPUTING OR CALCULATING; COUNTING > ELECTRIC DIGITAL DATA PROCESSING
AI Technology & Product Mapping
Technology Domain:
Memory Management & Data Routing
Product Category:
RAM Controllers & Memory Subsystems
Plain-English Summary:
Techniques specifically for shifting data bits or addresses within a system, such as adjusting positions or scaling.
Relation to Claims:
The abstract explicitly mentions a 'shift signal signifying that the first memory location is in the last column', triggering row indexing, which maps directly to internal address/data shifting operations.
CPC G11C7/00
Confidence: High
Official Definition
Arrangements for writing information into, or reading information out from, a digital store
PHYSICS > INFORMATION STORAGE > STATIC STORES
AI Technology & Product Mapping
Technology Domain:
Digital Memory Architecture
Product Category:
Dynamic RAM (DRAM) & Static RAM (SRAM) ICs
Plain-English Summary:
Circuits and architectural layouts used to write data into memory or read data out of memory.
Relation to Claims:
The entire patent focuses on reading data from a first memory location in a sub-array and writing it to the next sequential location, describing core read/write operations.
CPC G11C7/10
Confidence: Medium
Official Definition
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
PHYSICS > INFORMATION STORAGE > STATIC STORES
AI Technology & Product Mapping
Technology Domain:
Memory Interface & Control
Product Category:
Memory Integrated Circuits
Plain-English Summary:
Circuits and interfaces that manage how data enters and leaves a memory chip, including control logic and temporary buffers.
Relation to Claims:
The patent deals with externally generated row and column address signals and internal decoding to execute read and write operations across sub-arrays.
CPC G11C7/1006
Confidence: High
Official Definition
Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
PHYSICS > INFORMATION STORAGE > STATIC STORES
AI Technology & Product Mapping
Technology Domain:
Memory Internal Data Path
Product Category:
High-Speed RAM & Cache Controllers
Plain-English Summary:
Circuits that manage or manipulate data right before it is written into or read out of a memory array, including data routing switches.
Relation to Claims:
The patent describes internal data movement where data read from one sub-array location is automatically routed to write into the next sequential memory location without extra row addressing.