AI Patent Summary

Patent Document
#US5367484A
United States Patent 15)
Abstract
An erasable programmable memory device has a num- ber of data storage blocks. Each block has an endurance characteristic that at least roughly defines the number of times data may be erased from and written to the block before it wears out in that data cannot then be further erased from and written to the block. A redun- dant data storage block of memory capacity and endur- ance similar to that of each of the other data storage blocks is disposed in parallel with a selected one of the latter for which higher endurance is desired. This ena- bles identical data to be written simultaneously to the two blocks and thus considerably increases the endur- ance of the selected block by virtue of the fact that identical memory cells in both blocks must fail before the endurance of the selected block will be depleted. After the selected block has been designated for high endurance and placed in parallel with the redundant block, a fuse may be set to prevent alteration of that designation.
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Patent Classification & AI Product Mapping
Authoritative patent classification definitions mapped to real-world technology domains and commercial product categories.
CPC G11C29/00
Confidence: High
Official Definition
Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
PHYSICS > INFORMATION STORAGE > STATIC STORES
AI Technology & Product Mapping
Technology Domain:
Non-Volatile Memory Architecture
Product Category:
Flash Memory Management Systems
Plain-English Summary:
Methods and arrangements for monitoring memory health, testing data storage integrity, and repairing or improving faulty memory units.
Relation to Claims:
The patent deals with managing memory block endurance and lifespan, which aligns directly with addressing operational limits and reliability testing.
CPC G11C29/70
Confidence: High
Official Definition
Masking faults in memories by using spares or by reconfiguring
PHYSICS > INFORMATION STORAGE > STATIC STORES
AI Technology & Product Mapping
Technology Domain:
Non-Volatile Memory Architecture
Product Category:
Fault-Tolerant Memory Controllers
Plain-English Summary:
Techniques to hide or compensate for memory defects by utilizing spare memory cells or reconfiguring the storage layout.
Relation to Claims:
The disclosure describes assigning a redundant data storage block in parallel with a selected primary block to improve overall endurance and reliability.
CPC G11C29/74
Confidence: High
Official Definition
Masking faults in memories by using spares or by reconfiguring using duplex memories, i.e. using dual copies
PHYSICS > INFORMATION STORAGE > STATIC STORES
AI Technology & Product Mapping
Technology Domain:
Non-Volatile Memory Architecture
Product Category:
High-Reliability Flash Storage
Plain-English Summary:
Fault-tolerance methods in memories that rely on maintaining duplicate or twin copies of data across parallel memory blocks.
Relation to Claims:
The abstract explicitly details writing identical data simultaneously to two parallel blocks (the primary and a redundant block) to share wear and extend functional life.
CPC G11C16/00
Confidence: High
Official Definition
Erasable programmable read-only memories
PHYSICS > INFORMATION STORAGE > STATIC STORES
AI Technology & Product Mapping
Technology Domain:
Flash Memory Architecture
Product Category:
Non-Volatile Memory ICs
Plain-English Summary:
Memory devices that can be electrically or optically erased and reprogrammed multiple times, commonly known as EPROM, EEPROM, or Flash memory.
Relation to Claims:
The patent title and abstract explicitly target an 'erasable programmable memory device' having multiple data storage blocks with specific endurance limits.
CPC G11C16/02
Confidence: High
Official Definition
Erasable programmable read-only memories electrically programmable
PHYSICS > INFORMATION STORAGE > STATIC STORES
AI Technology & Product Mapping
Technology Domain:
Flash Memory Architecture
Product Category:
EEPROM and Flash Memory Chips
Plain-English Summary:
Semiconductor memory devices where data is erased and programmed purely through electrical signals, such as modern Flash memory and EEPROM.
Relation to Claims:
The invention discusses blocks that are erased and written to multiple times until they wear out, which is characteristic of electrically erasable programmable memories.