AI Patent Summary

Patent Document
#US5703809A
United States Patent 14
Abstract
A method of high speed reading of data from an EPROM, in which a memory array is programmed based on device status at intersections of rows and columns of the array to store data therein as 0’s and 1’s, uses a capacitive over- charging and discharging technique to enable fast voltage stabilization without drawing significant current. A row containing the memory element to be read is quickly over- driven to overcharge an effective capacitance associated with the row to substantially the maximum level of the EPROM supply voltage which may exceed the programmed threshold voltage of the selected memory element. The effective capacitance is thereupon discharged to a predeter- mined voltage level below both the maximum level of the supply voltage and the programmed threshold. Then the status and data content of the selected memory element are read by first grounding an electrode of a source-drain path of a transistor comprising the memory element to cause current with substantially no DC component to flow through that path of the transistor. A sense amplifier in the source-drain path of the transistor is triggered to detect current flow therethrough as indicative of the data content of the memory element.
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Patent Classification & AI Product Mapping
Authoritative patent classification definitions mapped to real-world technology domains and commercial product categories.
CPC G11C7/00
Confidence: High
Official Definition
Arrangements for writing information into, or reading information out from, a digital store
PHYSICS > INFORMATION STORAGE > STATIC STORES
AI Technology & Product Mapping
Technology Domain:
Non-Volatile Memory Architecture
Product Category:
Memory Integrated Circuits
Plain-English Summary:
General circuitry and methods for storing digital data into memory cells and retrieving stored data back out.
Relation to Claims:
The patent discloses a core read operation involving sensing current flow via a sense amplifier to determine data content, directly corresponding to general read arrangements for digital stores.
CPC G11C16/00
Confidence: High
Official Definition
Erasable programmable read-only memories
PHYSICS > INFORMATION STORAGE > STATIC STORES
AI Technology & Product Mapping
Technology Domain:
Non-Volatile Memory Architecture
Product Category:
EPROM and Flash Memory Chips
Plain-English Summary:
Memory devices that can retain data without power, be erased, and be reprogrammed.
Relation to Claims:
The invention explicitly targets the reading of data from an EPROM memory array.
CPC G11C16/02
Confidence: Medium
Official Definition
Erasable programmable read-only memories electrically programmable
PHYSICS > INFORMATION STORAGE > STATIC STORES
AI Technology & Product Mapping
Technology Domain:
Electrically Erasable Memory
Product Category:
EEPROM and Flash Storage Devices
Plain-English Summary:
Read-only memories that can be programmed and erased using electrical signals rather than ultraviolet light.
Relation to Claims:
The abstract discusses reading from an array programmed to store data as 0s and 1s, leveraging supply voltages and threshold voltages typical of EPROM technologies.
CPC G11C16/06
Confidence: High
Official Definition
Auxiliary circuits, e.g. for writing into memory
PHYSICS > INFORMATION STORAGE > STATIC STORES
AI Technology & Product Mapping
Technology Domain:
Memory Peripheral Circuitry
Product Category:
Memory Controller Subsystems
Plain-English Summary:
Supporting peripheral circuits used to manage operations inside memory chips, such as voltage generation or charge control.
Relation to Claims:
The abstract details a capacitive over-charging and discharging technique used to quickly stabilize row voltages without drawing excessive current, representing an auxiliary circuit function.
CPC G11C16/26
Confidence: High
Official Definition
Sensing or reading circuits; Data output circuits
PHYSICS > INFORMATION STORAGE > STATIC STORES
AI Technology & Product Mapping
Technology Domain:
Sense Amplifier & Read Circuitry
Product Category:
Memory Read Channels
Plain-English Summary:
Circuits designed to detect the state of memory cells and output the corresponding data values.
Relation to Claims:
The abstract explicitly describes triggering a sense amplifier in the source-drain path of a transistor to detect current flow as an indicator of the memory element's data content.