AI Patent Summary

Patent Document
#US5805507A
United States Patent 115
Abstract
A technique is disclosed for reading a memory element of an EPROM array embedded in a microcontroller chip which has been scaled down from a previous design by virtue of reduced line widths of a process technology used for fabri- cating the chip. The microcontroller chip has a predeter- mined supply voltage, and the array comprises rows and columns of addressable memory elements which may be selectively accessed to read data content therefrom in a low voltage mode in which the supply voltage initially rises and ultimately reaches substantially its maximum voltage during a read cycle. A regulated reference voltage is used to exercise row and column control in the low voltage read mode by tracking the level of the supply voltage up to a certain preselected level below the maximum supply voltage, and by clamping the row and column control voltage at substantially the preselected level despite increases in the level of the supply voltage above the preselected level.
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Patent Classification & AI Product Mapping
Authoritative patent classification definitions mapped to real-world technology domains and commercial product categories.
CPC G11C16/00
Confidence: High
Official Definition
Erasable programmable read-only memories
PHYSICS > INFORMATION STORAGE > STATIC STORES
AI Technology & Product Mapping
Technology Domain:
Non-Volatile Memory Architecture
Product Category:
EPROM & Flash Memory Devices
Plain-English Summary:
Memory chips that can be erased and reprogrammed, typically using electrical charges or ultraviolet light.
Relation to Claims:
The patent deals directly with reading memory elements within an EPROM array embedded in a microcontroller, which falls squarely into erasable programmable read-only memory technology.
CPC G11C16/02
Confidence: High
Official Definition
Erasable programmable read-only memories electrically programmable
PHYSICS > INFORMATION STORAGE > STATIC STORES
AI Technology & Product Mapping
Technology Domain:
Electrically Erasable Programmable Read-Only Memory (EEPROM)
Product Category:
Embedded Non-Volatile Memory ICs
Plain-English Summary:
Memory devices that can be programmed and erased strictly using electrical signals rather than external ultraviolet light sources.
Relation to Claims:
The abstract discusses reading memory elements in an EPROM array integrated on a microcontroller fabricated with scaled-down process technologies.
CPC G11C16/06
Confidence: High
Official Definition
Auxiliary circuits, e.g. for writing into memory
PHYSICS > INFORMATION STORAGE > STATIC STORES
AI Technology & Product Mapping
Technology Domain:
Memory Peripheral Circuitry
Product Category:
Microcontroller Subsystems
Plain-English Summary:
Support circuitry integrated alongside memory arrays used to manage operations like reading, writing, and voltage regulation.
Relation to Claims:
The invention employs a regulated reference voltage to exercise row and column control during a low-voltage read mode, representing a primary auxiliary circuit function.
CPC G11C16/30
Confidence: High
Official Definition
Power supply circuits
PHYSICS > INFORMATION STORAGE > STATIC STORES
AI Technology & Product Mapping
Technology Domain:
Integrated Circuit Power Management
Product Category:
Voltage Regulators & Power Control Blocks
Plain-English Summary:
Circuits that manage, regulate, or distribute internal power and voltages used by memory chips during operation.
Relation to Claims:
The patent centers on handling low-voltage modes where supply voltage rises and is tracked/clamped using a regulated reference voltage for row and column control.
CPC G11C5/00
Confidence: Medium
Official Definition
Details of stores covered by group G11C11/00
PHYSICS > INFORMATION STORAGE > STATIC STORES
AI Technology & Product Mapping
Technology Domain:
Semiconductor Memory Design
Product Category:
Microcontrollers & SoCs
Plain-English Summary:
General structural details, layouts, and physical implementations of digital memory stores and arrays.
Relation to Claims:
The patent addresses structural implementations of memory arrays embedded within a microcontroller chip scaled down via reduced line widths.