AI Patent Summary

Patent Document
#US5812456A
United States Patent 115
Abstract
A technique for reading data from a selected memory element of an EPROM array having rows and columns with addressable memory elements which may be selectively accessed at respective intersections of the rows and columns. Each memory element includes a transistor having gate, source and drain electrodes, and after selection of a particu- lar memory element from which data is to be read by appropriately biasing the row and column associated with that memory clement, the source electrode thereof is selec- tively connected to ground by a switching element to allow current flow through the source-drain path of the memory element and enable the readout of data therefrom after the drain and gate voltages of the memory element have stabi- lized.
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Patent Classification & AI Product Mapping
Authoritative patent classification definitions mapped to real-world technology domains and commercial product categories.
CPC G11C16/00
Confidence: High
Official Definition
Erasable programmable read-only memories
PHYSICS > INFORMATION STORAGE > STATIC STORES
AI Technology & Product Mapping
Technology Domain:
Non-Volatile Memory Architecture
Product Category:
EPROM and Flash Memory Chips
Plain-English Summary:
Memory chips that can retain data without power, erase stored information using specific signals (like ultraviolet light or electrical voltages), and be reprogrammed with new data.
Relation to Claims:
The patent deals with an EPROM memory array having rows, columns, and individual transistor memory elements, directly mapping to the general architecture of erasable programmable read-only memories.
CPC G11C16/02
Confidence: High
Official Definition
Erasable programmable read-only memories electrically programmable
PHYSICS > INFORMATION STORAGE > STATIC STORES
AI Technology & Product Mapping
Technology Domain:
Electrically Erasable Programmable Memory
Product Category:
EEPROM and Flash Memory Devices
Plain-English Summary:
Memory devices that use electrical signals to program or write data into the memory cells, rather than relying on external exposure like ultraviolet light.
Relation to Claims:
The patent references memory elements with gate, source, and drain electrodes that are selectively biased to perform reading operations, aligning with electrically addressable memory designs.
CPC G11C16/06
Confidence: Medium
Official Definition
Auxiliary circuits, e.g. for writing into memory
PHYSICS > INFORMATION STORAGE > STATIC STORES
AI Technology & Product Mapping
Technology Domain:
Memory Peripheral Circuitry
Product Category:
Memory Integrated Circuit Components
Plain-English Summary:
Support circuitry integrated onto a memory chip that assists with primary memory operations like writing, reading, or biasing cells.
Relation to Claims:
The technique involves appropriately biasing rows and columns and utilizing switching elements to selectively connect source electrodes to ground, which constitutes auxiliary control circuitry.
CPC G11C16/26
Confidence: High
Official Definition
Sensing or reading circuits; Data output circuits
PHYSICS > INFORMATION STORAGE > STATIC STORES
AI Technology & Product Mapping
Technology Domain:
Memory Sensing and Read-Out Systems
Product Category:
Memory Controllers and Read Channels
Plain-English Summary:
Electronic circuits designed to detect, amplify, and output the data stored within a memory cell by measuring current or voltage levels.
Relation to Claims:
The abstract explicitly focuses on a technique for reading data from a selected memory element by allowing current flow through the source-drain path to enable readout after voltages stabilize.
CPC G11C16/30
Confidence: Medium
Official Definition
Power supply circuits
PHYSICS > INFORMATION STORAGE > STATIC STORES
AI Technology & Product Mapping
Technology Domain:
Power Management for Memory
Product Category:
Integrated Voltage Regulators and Bias Generators
Plain-English Summary:
Internal circuits that manage, deliver, or regulate voltages and currents supplied to memory cells during operations like reading or writing.
Relation to Claims:
The invention relies on appropriately biasing the row, column, gate, and drain voltages, and stabilizing these voltages to enable accurate data readout.