AI Patent Summary

Patent Document
#US6728856B2
United States Patent
Abstract
A processor has an architecture that provides the processing speed advantages of the Harvard architecture, but does not require special purpose instructions or two separate external memories in order to expand both data memory and program instruction memory. The processor has separate program memory space and data memory space, but provides the capability to map at least a portion of the program memory space to the data memory space. This allows most program instructions that are processed to obtain the speed advan- tages of simultaneous program instruction and data access, yet provides a means to access program memory resident data without special purpose instructions. It also allows program memory space and data memory space to be expanded externally to the processor using only one external memory device that includes both program instructions and data. The processor includes a program memory space operable to store program instructions and data, a data memory space operable to store data, and mapping circuitry operable to map at least a portion of the program memory space to the data memory s; The program memory space may be internal to the processor. The processor may further comprise a page register operable to specify a location of the program memory space that is mapped to the data memory space. 13 Claims, 4 Drawing Sheets 100 “PROCESSOR £105 “PROG. MEMORY | cite | Es FETCH OECODE Fits | iNsTRUGTION EXECUTION UNITS ~~ WREGISTERS. DATA MEMORY (XANDIOR ¥) AND W REGISTERS 15 PHERALS
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Patent Classification & AI Product Mapping
Authoritative patent classification definitions mapped to real-world technology domains and commercial product categories.
CPC G06F9/00
Confidence: High
Official Definition
Arrangements for program control, e.g. control units
PHYSICS > COMPUTING OR CALCULATING; COUNTING > ELECTRIC DIGITAL DATA PROCESSING
AI Technology & Product Mapping
Technology Domain:
Embedded Systems & Microcontrollers
Product Category:
Microcontrollers & SoCs
Plain-English Summary:
Hardware mechanisms and circuitry responsible for directing the operation of the processor, fetching instructions, and managing the flow of control.
Relation to Claims:
The patent outlines a processor architecture with a control mechanism that manages separate program and data memory spaces while allowing mapping between them.
CPC G06F9/06
Confidence: High
Official Definition
Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
PHYSICS > COMPUTING OR CALCULATING; COUNTING > ELECTRIC DIGITAL DATA PROCESSING
AI Technology & Product Mapping
Technology Domain:
Processor Architecture
Product Category:
Microcontrollers & SoCs
Plain-English Summary:
Stored-program computer architecture where instructions are held in an internal memory unit within the processor hardware.
Relation to Claims:
The patent describes internal program memory spaces and data memory spaces used to execute stored program instructions efficiently.
CPC G06F9/30
Confidence: High
Official Definition
Arrangements for executing machine instructions, e.g. instruction decode
PHYSICS > COMPUTING OR CALCULATING; COUNTING > ELECTRIC DIGITAL DATA PROCESSING
AI Technology & Product Mapping
Technology Domain:
Instruction Set Architecture
Product Category:
Microprocessors
Plain-English Summary:
Circuits and logic used to decode and execute specific machine-level instructions within a processor.
Relation to Claims:
The processor processes program instructions to obtain speed advantages, utilizing specialized mapping to access program memory resident data without special-purpose instructions.
CPC G06F9/38
Confidence: High
Official Definition
Concurrent instruction execution, e.g. pipeline or look ahead
PHYSICS > COMPUTING OR CALCULATING; COUNTING > ELECTRIC DIGITAL DATA PROCESSING
AI Technology & Product Mapping
Technology Domain:
High-Performance Processor Design
Product Category:
Central Processing Units (CPUs)
Plain-English Summary:
Techniques that allow a processor to process multiple instructions or fetch data and instructions simultaneously to speed up execution.
Relation to Claims:
The abstract explicitly highlights providing the processing speed advantages of simultaneous program instruction and data access inherent in modified Harvard architectures.
CPC G06F9/3802
Confidence: Medium
Official Definition
Instruction prefetching
PHYSICS > COMPUTING OR CALCULATING; COUNTING > ELECTRIC DIGITAL DATA PROCESSING
AI Technology & Product Mapping
Technology Domain:
Processor Memory Subsystems
Product Category:
Microcontrollers & SoCs
Plain-English Summary:
Mechanisms that fetch instructions from memory into the processor before they are actually needed, reducing waiting time.
Relation to Claims:
The processor architecture incorporates instruction fetch units and mapping circuitry to optimize memory retrieval speeds.