Results

A controller and a method is provided for controlling a capacitance of an LC circuit having a circuit frequency including, a variable capacitor to couple with an external inductor as part of an LC circuit, a target value, a spread spectrum function to generate an adjustment value, and a circuit to poll the target value, call the spread spectrum function, and set a capacitance of the variable capacitor based on the sum of the target value and the adjustment value. 19 Claims, 5 Drawing Sheets

A system includes non-transitory computer readable memory and a processor. The non-transitory computer read- able memory stores a current processor interrupt priority level and a current disable interrupt control (DISICTL) interrupt priority level. ‘The processor to update the current processor interrupt priority level based on respective inter- rupt priority levels associated with respective exceptions, and update the current DISICTL interrupt priority level based on a respective DISICTL instruction, wherein the respective DISICTL instruction specifies a respective user- definable DISICTL interrupt priority level. The processor determines a highest interrupt priority level between the current processor interrupt priority level and the current DISICTL interrupt priority level, and apply the highest interrupt priority level during execution of respective code. 20 Claims, 7 Drawing Sheets fe. 00 / ¥ RSOCESSOR IPL DISICTL IPL NSTRUCTIONS ‘OCESSOR IPL

A fault event monitor and filter having a digital comparator receiving a digital input value, wherein the digital compara- tor generates a plurality of outputs based on programmable threshold input values, a first counter coupled to a first output of the plurality of outputs of the digital comparator, a second counter coupled to a second output of the plurality of outputs of the digital comparator, and an output controller with a first input coupled to an output of the first counter and with a second input coupled to an output of the second counter, wherein the output controller to generate a fault event signal based at least partially on signals received from the first and second counters. 9 Claims, 5 Drawing Sheets

A temperature sensor integrated in a transistor array, e.g., metal-oxide-semiconductor field-effect transistor (MOS- FET) array, is provided. The integrated temperature sensor may include a doped well region formed in a substrate (e.g., SiC substrate), a resistor gate formed over the doped well region, first and second sensor terminals conductively coupled to the doped well region on opposite sides of the resistor gate. The integrated temperature sensor includes a gate driver to apply a voltage to the resistor gate that affects a resistance of the doped well region below the resistor gate, and temperature analysis circuitry to determine a resistance of a conductive path passing through the doped well region, and determine a temperature associated with the transistor array. 21 Claims, 13 Drawing Sheets

A device including an input to receive a clock signal, a ramp start program register, a ramp start active register, a ramp stop program register, a ramp stop active register, a ramp slope program register, a ramp slope active register, an update controller, the update controller to update, based on a programmable condition, respectively, the ramp start active register contents, the ramp stop active register con- tents and the ramp slope active register contents, and a ramp controller to generate a ramp signal, the ramp signal to begin at the value reflective of the ramp start active register contents, the ramp signal to change value at each cycle of the clock signal based on the value reflective of the ramp slope active register contents, and the ramp signal to stop at the value reflective of the ramp stop active register contents. 23 Claims, 5 Drawing Sheets 100 y g MP 03 105 Vout