A system includes non-transitory computer readable memory and a processor. The non-transitory computer read- able memory stores a current processor interrupt priority level and a current disable interrupt control (DISICTL) interrupt priority level. ‘The processor to update the current processor interrupt priority level based on respective inter- rupt priority levels associated with respective exceptions, and update the current DISICTL interrupt priority level based on a respective DISICTL instruction, wherein the respective DISICTL instruction specifies a respective user- definable DISICTL interrupt priority level. The processor determines a highest interrupt priority level between the current processor interrupt priority level and the current DISICTL interrupt priority level, and apply the highest interrupt priority level during execution of respective code. 20 Claims, 7 Drawing Sheets fe. 00 / ¥ RSOCESSOR IPL DISICTL IPL NSTRUCTIONS ‘OCESSOR IPL

A fault event monitor and filter having a digital comparator receiving a digital input value, wherein the digital compara- tor generates a plurality of outputs based on programmable threshold input values, a first counter coupled to a first output of the plurality of outputs of the digital comparator, a second counter coupled to a second output of the plurality of outputs of the digital comparator, and an output controller with a first input coupled to an output of the first counter and with a second input coupled to an output of the second counter, wherein the output controller to generate a fault event signal based at least partially on signals received from the first and second counters. 9 Claims, 5 Drawing Sheets

A temperature sensor integrated in a transistor array, e.g., metal-oxide-semiconductor field-effect transistor (MOS- FET) array, is provided. The integrated temperature sensor may include a doped well region formed in a substrate (e.g., SiC substrate), a resistor gate formed over the doped well region, first and second sensor terminals conductively coupled to the doped well region on opposite sides of the resistor gate. The integrated temperature sensor includes a gate driver to apply a voltage to the resistor gate that affects a resistance of the doped well region below the resistor gate, and temperature analysis circuitry to determine a resistance of a conductive path passing through the doped well region, and determine a temperature associated with the transistor array. 21 Claims, 13 Drawing Sheets

A device including an input to receive a clock signal, a ramp start program register, a ramp start active register, a ramp stop program register, a ramp stop active register, a ramp slope program register, a ramp slope active register, an update controller, the update controller to update, based on a programmable condition, respectively, the ramp start active register contents, the ramp stop active register con- tents and the ramp slope active register contents, and a ramp controller to generate a ramp signal, the ramp signal to begin at the value reflective of the ramp start active register contents, the ramp signal to change value at each cycle of the clock signal based on the value reflective of the ramp slope active register contents, and the ramp signal to stop at the value reflective of the ramp stop active register contents. 23 Claims, 5 Drawing Sheets 100 y g MP 03 105 Vout

An apparatus includes a debugger circuit, debug pins, and a test controller circuit. The test controller circuit is configured to, ina programming mode, determine a subset of the debug pins used in programming the apparatus. The test controller circuit is further configured to save a designation of the subset of the debug pins. The test controller circuit is further configured to, in a test mode subsequent to the programming mode, use the designation to route the subset of the debug pins used in programming the apparatus to the debugger circuit for debug input and output with the server. 15 Claims, 3 Drawing Sheets

One or more examples relate, generally, to reducing error in estimated angular position of a rotor of a motor. In one example, a method comprises generating an error signal indicating error in the estimated angular position; determin- ing an adjustment amount associated with an estimated torque-producing component of motor winding current of a stator of the motor; generating an adjustment signal corre- sponding to the determined adjustment amount; and com- bining the error signal and the adjustment signal to generate a corrected error signal. 17 Claims, 8 Drawing Sheets ft ico ¥

One or more examples relate, generally, to an orientation of a rotor. Some examples relate to an apparatus. The apparatus may include sample-accumulation logic to generate, over a time duration, a value indicative of inductance at least partially responsive to a probe signal provided to a stator of a motor. The apparatus may also include a probe-current discriminator to generate a further value indicative of an orientation of a rotor of the motor at least partially respon- sive to the generated value. The apparatus may also include update logic to update a process variable of a control loop at least partially responsive to a state of the further value. 21 Claims, 11 Drawing Sheets

Asystem and method of testing an integrated circuit provide a first clock signal to a first flip-flop with an output to a functional circuit, provide a second clock signal to a second flip-flop with an input from the functional circuit, wherein the second flip-flip has a minimum hold time, provide a test input to the first flip-flop, observe a signal propagation time through the functional circuit, determine the signal propa- gation time is less than the minimum hold time of the second flip-flop, and increasing a timing separation by adding a unit of delay to the first clock signal or subtracting a unit of delay from the second clock 2 20 Claims, 7 Drawing Sheets

Object detection for wireless power transmitters and related systems, methods, and devices are disclosed. A controller for a wireless power transmitter is configured to receive a measurement voltage potential responsive to a tank circuit signal at a tank circuit, provide an alternating current (AC) signal to each of the plurality of transmit coils one at a time, and determine at least one of a resonant frequency and a quality factor (Q-factor) of the tank circuit responsive to each selected transmit coil of the plurality of transmit coils. The controller is also configured to select a transmit coil to use to transmit wireless power to a receive coil of a wireless power receiver responsive to the determined at least one of the resonant frequency and the Q-factor for each transmit coil of the plurality of transmit coils. 20 Claims, 10 Drawing Sheets

An article of manufacture includes a non-transitory machine-readable medium. ‘The medium includes instruc- tions that cause a processor to execute a shift instruction. The shift instruction is to cause a source data in memory to be shifted left or shifted right. The shift instruction is to include a source parameter and a bit size parameter. The processor is to execute the shift instruction through a shift of a first source word of the source data by the bit size parameter to yield a first intermediate word, a shift of a second source word of the source data by the bit size parameter to yield a second intermediate word and a first set of shifted-out bits, and through execution of a logical OR operation on the first intermediate word and the first set of shifted-out bits to yield a first result word. 20 Claims, 6 Drawing Sheets Destination Register “Size =M Words} I Nih sig, L2t2N _ Destination Word 202~ r, b— Processor

Foreign object detection for wireless power transmission and related systems, methods, and devices are disclosed. A controller for a wireless power transmitter is to determine a transmit coil voltage potential at a transmit coil of the wireless power transmitter, determine an input power pro- vided to the wireless power transmitter, determine a trans- mitter power loss, and determine a transmitted power of the wireless power transmitted to the wireless power receiver based, at least in part, on the input power and the transmitter power loss. The controller is also to compute a power loss responsive to the transmitted power and a received power indicated by the wireless power receiver, and determine that a foreign object is detected responsive to a determination that the power loss is greater than a predetermined threshold. 16 Claims, 11 Drawing Sheets

An apparatus may include a processor. The apparatus may include a memory communicatively coupled to the proces- sor. The apparatus may include a memory control circuit (MCC). The MCC may be configured to define a protected portion of the memory, wherein the protected portion of the memory is configured for read-only access by the processor, increase a size of the protected portion of the memory, and, after the increase in size of the protected portion of the memory, prevent decreases of the size of the protected portion of the memory. 20 Claims, 4 Drawing Sheets 114 198.118,120,122 Ne) , | 126 440

An EtherCAT device is disclosed. The EtherCAT device comprises a data input port to receive a signal representing data, the signal representing one of a plurality of possible logical values; and a degradation calculation circuit. The degradation calculation circuit is to read, demodulate, < convert the received signal into a digital domain repre: tation; process the digital domain representation into slices, where the value of the received signal at a respective time is represented in a respective one of the slices; determine differences between the respective slices and reference slices; identify an intended logical value of the received signal responsive to the determined differences; determine a quantification of error at the respective time responsive to the identified logical value and the determined differences:

An apparatus includes a single sense pin connected to a line of a device connected to the apparatus, a gate pin configured to produce a gate signal to enable or disable a switch connected between the line of the device connected to the apparatus and a system ground, and control logic. The control logic is configured to at the single sense pin, deter- mine a short between the device and the system ground, and, based upon the determination of the short, disable the switch. 17 Claims, 5 Drawing Sheets

A computer system includes a non-transitory computer- readable memory to store (a) a vector table including an exception vector pointing to an exception handler and (b) a vector fail address of a vector fetch bus error handler, and a processor to identify an exception, initiate an exception vector fetch in response to the identified exception to read the exception vector from the vector table, identify a vector fetch bus error associated with the exception vector fetch, access the vector fail address of the vector fetch bus error handler in response to the vector fetch bus error, and execute the vector fetch bus error handler.

Disclosed examples include an apparatus. The apparatus may include a differential signal path portion, a first circuit, and a second circuit. The first circuit may be arranged at the differential signal path portion to set a differential imped- ance of the differential signal path portion. The second circuit may be arranged outside of the differential signal path portion to set a common-mode impedance of the differential signal path portion lower than the differential impedance. 18 Claims, 5 Drawing Sheets

Apparatuses and methods related to a converter are dis- closed. An apparatus includes a converter and a controller. The converter converts an input voltage potential to an output voltage potential. The input voltage potential and the output voltage potential include direct current (DC) voltage potentials. The controller generates pulse width modulation (PWM) signals responsive to a duty cycle control signal, controls the converter via the PWM signals in a buck mode when the duty cycle control signal is less than a predeter- mined maximum buck value, and controls the converter via the PWM signals in a cascaded buck-boost mode (CBB mode) when the duty cycle control signal is greater than the predetermined maximum buck value. A duty cycle of at least a portion of the PWM signals transitions linearly with the duty cycle control signal from the buck mode to the CBB mode.

Aburn-in board for burn-in testing of semiconductor devices includes a strip socket mounted to a PCB. The strip socket includes a socket base configured to receive a device strip including an array of semiconductor devices, and a socket lid including at least one heating block. The socket lid is movable moved between (a) an open position allowing the device strip to be mounted on the socket base and (b) a closed position in which the socket lid including the heating block(s) is closed down on the mounted device strip. The strip socket includes conductive contacts configured to con- tact individual semiconductor devices on the device strip to allow selective monitoring of individual semiconductor devices during a burn-in test process. The burn-in board may also include heating control circuitry to control the heating block(s) during the burn-in test process. 21 Claims, 22 Drawing Sheets

A method and apparatus for measuring an unknown imped- ance. The apparatus comprises a first input to receive a first signal generated by a first portion of a sensor circuit, the first portion comprising an unknown impedance and a first known resistance, the unknown impedance to vary based upon a phenomenon to be measured by the sensor circuit. The apparatus also comprises a second input to receive a second signal generated by a second portion of the sensor circuit, the second portion of the sensor circuit comprising, a known impedance and a second known resistance. And the apparatus comprises control logic to, based on a difference in time at which each of the first input and the second input reach a reference voltage, determine a measurement of the sensor circuit. 20 Claims, 9 Drawing Sheets ? t i { i i | | patie es, { » S \

A curvature compensated bandgap circuit that is capable of matching best-in-c two (2) parts-per-million perfor- mance without over-temperature trimming. This improves performance metrics for precision voltage reference prod- ucts without requiring individual device tuning during pro- duction thereof. A core bandgap circuit comprises a main operational amplifier having a second order bowed voltage response over temperature. A ptat circuit is coupled to the core bandgap circuit to provide a sigmoidal third order shape for the bandgap voltage. 13 Claims, 4 Drawing Sheets

A PWM lighting bridge manages hardware PWM compen- sation components. One or more PWM outputs are driven based upon a master PWM input signal. The master PWM input signal is processed through a mapping function to produce a desired output signal(s) on the one or more PWM outputs. The mapping function comprises a set of compen- sation bins having a maxim input duty cycle, a minimum input duty cycle and an output duty cycle. The mapping process selects a bin based on determining whether the input duty cycle is within the minimum and maximum duty cycle ranges of the bins and then uses the specified output duty cycle for the one or more PWM outputs. The PWM lighting bridge provides configuration and runtime management of the hardware PWM compensation components. Read/write access to the PWM compensation bins provides customiz- able configurations of the input and output PWM charac- teristics. 21 Claims, 5 Drawing Sheets : PWM Outputs

An apparatus includes an adjustment circuit configured to receive a pulsed-width modulation (PWM) input, generate an adjusted PWM signal based upon the PWM input, and determine that a first pulse of the PWM input is shorter than a runt signal limit. The adjustment circuit is further config- ured to, in the adjusted PWM signal, extend the first pulse of the PWM input based on the determination that the PWM input is shorter than the runt signal limit, and output the adjusted PWM signal to an electronic device. 9 Claims, 9 Drawing Sheets te

An apparatus is provided comprising a first t-switch, which includes an input port arranged to be connected to a first voltage source, a center-tap port, and an output port arranged to be connected to a load. The first t-switch is configured to connect the input port to the output port in an on mode and disconnect the input port from the output port in an off mode. The apparatus further comprises a bias voltage generation circuit configured to generate a bias voltage, the generated bias voltage coupled to the center-tap port of the first t-switch, the bias voltage determined based upon an output port voltage. 20 Claims, 6 Drawing Sheets 106 — Load VB 80 VS=VB TT 2] B+VOS) 108 B+VOS, \VB+VOS |

Examples disclosed herein include a speaker. The speaker may include a group of microphones and a processor. The processor may determine a first speaker-channel identifier for a multi-speaker system at least partially responsive to a first tone captured at the group of microphones. The pro- cessor may also determine a position of a source of the captured first tone relative to the speaker at least partially responsive to position information derived from the captured first tone. The processor may also determine a second speaker-channel identifier at least partially responsive to the first speaker-channel identifier and the position of the source of the captured first tone. The processor may also determine speaker settings at least partially responsive to the second speaker-channel identifier. Related devices, systems and methods are also disclosed.

A system for managing a virtual meeting (e.g., video con- ference) includes memory storing a video conference appli- cation and at least one processor to execute the video conference application to generate a virtual meeting view for a first attendee including multiple attendee video streams arranged according to a virtual attendee arrangement speci- fying positions of the attendee video streams relative to each other in the virtual meeting view, receive second attendee audio data associated with a second attendee video stream, identify a particular video stream position specified by the virtual attendee arrangement, determine differential stereo effect data corresponding with the particular video stream position, and apply the differential stereo effect data to the second attendee audio data to provide differential audio signals on different audio channels output to the first attendee to create a stereo sound effect corresponding with the particular video stream position. 27 Claims, 8 Drawing Sheets

Lead frames for semiconductor device packages may include lead fingers proximate to a die-attach pad. A convex corner of the lead frame proximate to a geometric center of the lead frame may be rounded to include a radius of curvature of at least two times a greatest thickness of the die-attach pad. The thickness of the die-attach pad may be measured in a direction perpendicular to a major surface of the die-attach pad. A shortest distance between the die-attach pad and each one of the lead fingers having a surface area larger than an average surface area of the lead fingers may be at least two times the greatest thickness of the die-attach pad. 20 Claims, 5 Drawing Sheets 304 «308 308 bz #9 we 62

Apparatus and methods of automatically trimming a PCB- based LC circuit. The apparatus may comprise an interface to a printed circuit board (PCB). The PCB may include a PCB inductor and a PCB capacitor to form an LC circuit. The LC circuit may have an LC circuit frequency. The apparatus may comprise a variable capacitor communica- tively coupled to the interface and configured to adjust an effective capacitance of the LC circuit. 19 Claims, 3 Drawing Sheets ae 118 ] ft ———e | oT ar 464 4: 3 ay vrei} TouchiProximity | 7 32 i Detection Circuitr | 35 ‘ ' st } i C i 4 ; LPCB $0

An apparatus includes a database with device profiles, and a device programmer. The device programmer includes instructions. The instructions, when read and executed by a processor, cause the device programmer to identify a device identifier of an electronic device. The device programmer is further caused to, based upon the device identifier, access device data from the database. The device programmer is further caused to, based upon the device data, determine an area of memory of the electronic device that can be written. The device programmer is further caused to, based on the determination of the area of memory of the electronic device that can be written, write data to the area of memory. 21 Claims, 4 Drawing Sheets 400 ve

An apparatus includes an adjustment circuit configured to receive a pulsed-width modulation (PWM) input, generate an adjusted PWM signal based upon the PWM input, and determine that a first pulse of the PWM input is shorter than a runt signal limit. The adjustment circuit is further config- ured to, in the adjusted PWM signal, extend the first pulse of the PWM input based on the determination that the PWM input is shorter than the runt signal limit, and output the adjusted PWM signal to an electronic device. 18 Claims, 9 Drawing Sheets